All chips use CMOS 10S chip technology, except for the clock chip (CMOS 8S). CMOS 10S is state-of-the-art microprocessor technology based on ten-layer Copper Interconnections and Silicon-On Insulator technologies. The chip lithography line width is 0.125 micron.

The eight PU chips come in two versions. For the z9 EC models S08, S18, S28, and S38, the Processor Units (PUs) on the MCM in each book are implemented with a mix of single-core and dual-core PU chips. Four single-core and four dual-core chips are used, resulting in 12 PUs per MCM.

For the z9 EC Model S54 the Processor Units (PUs) on the MCMs in all books are implemented with eight dual-core PU chips, resulting in 16 PUs per MCM.

Eight to ten PUs of the 12 PU version may be characterized for customer use. The two standard SAPs are initially allocated to the dual-core processor chips. Optionally, up to two spare chips may be allocated on an MCM. System-wide, two spare chips are available that may be allocated on any MCM of the system. Each core on the chip runs at a cycle time of 0.58 nanoseconds. Each dual-core PU chip measures 15.78 x 11.84 mm and has 121 million transistors.

In the 16 PU version, used in all MCMs of a z9 EC Model S54, 12 to 14 PUs are available for customer use. Optionally, up to two spare chips may be allocated on an MCM. System-wide, two spare chips are available that may be allocated on any MCM of the system.

Each PU has a 512 KB on chip Level 1 cache (L1) that is split into a 256 KB L1 cache for instructions and a 256 KB L1 cache for data, providing large bandwidth.

The L1 caches communicate with the L2 caches (SD chips) by two bi-directional 16-byte data buses. There is a 2:1 bus/clock ratio between the L2 cache and the PU, controlled by the Storage Controller (SC chip), that also acts as an L2 cache cross-point switch for L2-to-L2 ring traffic, L2-to-MSC traffic, and L2-to-MBA traffic. The L1-to-L2 interface is shared by two PU cores on a dual core PU chip. The SC chip measures 16.41 x 16.41 mm and has 162 million transistors.

The Level 2 cache (L2) is implemented on the four System Data (SD) cache chips, each with a capacity of 10 MB, providing a cache size of 40 MB. These chips measure 15.66 x 15.40 mm and carry 660 million transistors, making it one of the world’s densest chips.

MSC chip

Two Memory Storage Control (MSC) chips police traffic between memory (PMAs) and the Level 2 cache. The MSC chips measures 14.31 x 14.31 mm and each have 24 million transistors.  The dual-core PU chips share the path to the MSC chip (L2 control) and the clock chip (CLK).