Two concentric loops or rings are constructed (one flowing clock-wise, and one flowing counter clock-wise) such that in a four-book system each book only is connected to two others, which means that only data transfers or data transactions to the third book require passing through one of the other books.

Book-to-book communications are organized as shown in Figure 2-4. Book 0 communicates with book 2 and book 3; communication to book 1 must go through another book (either book 2 or book 3). In a two or three book configuration, jumper books complete the ring.

A memory-coherent director optimizes ring traffic and filters out cache traffic by not looking on the ring for cache hits in other books if it is certain that the resources for a given logical partition exist in the same book.

The Level 2 (L2) cache is implemented on four cache (SD) chips. Each SD chip holds 10 MB, resulting in a 40 MB L2 cache per book. The L2 cache is shared by all PUs in the book and has a store-in buffer design. The connection to processor memory is done through four high-speed memory buses.

There is a ring structure within which the books maintain inter-book communication at the L2 cache level.  Additional books extend the function of the ring structure for inter-book communication. A simplified ring topology for 2, 3, and book systems is shown in Figure 2-5.  A book jumper completes the ring in order to be able to insert additional books into the ring non-disruptively.